1. Field of the Invention
The present invention relates to a discrete Fourier transform (DFT) filter bank, and more particularly to a polyphase filter bank with stack shift capability which can be implemented with significantly less hardware than known filter banks.
2. Description of the Prior Art
Digital filter banks are generally known in the art. Examples of such digital filter banks are disclosed in U.S. Pat. Nos. 4,107,470; 4,393,456; 4,792,943; 4,839,889; 5,436,940; and 5,606,575, hereby incorporated by reference. Such digital filter banks are implemented with digital signal processors and are used in a wide variety of applications including telecommunications applications, for example, cellular telephone applications.
Such digital filter banks are known to be used as spectrum analyzers as illustrated in FIG. 1A and frequency synthesizers, as illustrated in FIG. 1B as discussed in detail in Multi-Rate Digital Signal Processing, by Ronald E. Crochiere and Lawrence R. Rabiner, Prentice Hall, copyright 1983, hereby incorporated by reference. As is generally known in the art, the principles relating to frequency synthesizers are normally applicable to spectrum analyzers and vice versa.
Referring to FIG. 1A, a broad-band input signal x(n) is applied to a digital filter bank, configured as a spectrum analyzer, which divides the input signal x(n) into K frequency channels, 0 through K−1, which correspond to K output signals x0(m), x1(m) . . . xk(m) . . . xK−1(m).
Similarly, the system illustrated in FIG. 1B may be used to synthesize a plurality of input signals x0(m), x1(m) . . . xk(m) . . . xK−1(m), defining K input channels, 0 through K−1. In this embodiment, K input signals x0(m), x1(m) . . . xK−1(m) representing K channels 0 through K−1 are synthesized by the digital filter bank to form a broad-band output signal x(n).
FIGS. 2A and 2B represent models for a DFT filter bank analyzer and a DFT filter bank synthesizer, respectively, as set forth in Multi-Rate Digital Signal Processing, supra. For simplicity, only a single channel is illustrated. As illustrated in FIGS. 2A and 2B, the sampling frequency of the analyzer is decimated or decreased while the sampling frequency for the synthesizer is interpolated or increased. As such, such DFT digital filter banks are multi-rate in nature.
As shown in FIGS. 2A and 2B, the DFT filter banks are modeled by a low pass filter h(n), f(n) and a complex modulator. In addition, as discussed above, the sampling frequency is either decimated by a factor M as in the case of a filter bank analyzer or interpolated by a factor M in the case of a filter bank synthesizer. As shown in FIG. 2A, in the case of the analyzer, an input signal x(n) is modulated by a complex modulator of the form e−jωkn and low pass filtered by a filter h(n). The sampling rate is then reduced or decimated by a factor M to generate the channel signals xk(m). The filter h(n) determines the width and the frequency response of each of the channels. The filters h(n) for each channel are identical.
For a DFT filter bank with uniformly spaced filters and even type stacking arrangements, the center frequency of each of the channels is given by equation 1 below:
                                          ω            k                    =                                    2              ⁢                                                          ⁢              π              ⁢                                                          ⁢              k                        K                          ,                  k          =          0                ,        1        ,        …        ⁢                                  ,                  K          -          1                                    (        1        )            By defining WK=ej(2π/K) the complex modulation function can be rewritten as shown in equation 2 below:
                              ⅇ                                    -                                                j                  ⁢                                                                                                          ω                  ⁢                                                                          ⁢                  k                                                      ⁢            n                          =                              ⅇ                                          -                j2π                            ⁢                                                          ⁢              k              ⁢                                                          ⁢              n              ⁢                              /                            ⁢              K                                =                      W            K                          -              kn                                                          (        2        )            The channel signals may then be expressed as set forth in equation 3:
                                                        X              K                        ⁡                          (              m              )                                =                                    ∑                              n                =                                  -                  ∞                                            ∞                        ⁢                                                  ⁢                                          h                ⁡                                  (                                      mM                    -                    n                                    )                                            ⁢                              x                ⁡                                  (                  n                  )                                            ⁢                              W                K                                  -                  kn                                                                    ,                  k          =          0                ,        1        ,        …        ⁢                                  ,                  K          -          1                                    (        3        )            
With respect to the DFT filter bank synthesizer, for example as shown in FIG. 2B, all of the input channel signals x0(m), x1(m) . . . xk(m) . . . xK−1(m) are interpolated to a higher sampling rate and modulated back to the original spectral location. The synthesizer then adds all of the channel signals together to produce a single output signal x(n). Each of the input channel signals x0(m), x1(m) . . . xk(m) . . . xK−1(m) are interpolated by a factor M and filtered with an interpolation filter f(n) and modulated by a complex modulation function WK−kn=e−jωkn to shift the channel signal back to its original location ωk. Equation 4 represents the output of each channel signal:
                                                                        x                ^                            k                        ⁡                          (              n              )                                =                                    W              K              kn                        ⁢                                          ∑                                  m                  =                                      -                    ∞                                                  ∞                            ⁢                                                                                          X                      ^                                        k                                    ⁡                                      (                    m                    )                                                  ⁢                                  f                  ⁡                                      (                                          n                      -                      mM                                        )                                                                                      ,                  k          =          0                ,        1        ,        …        ⁢                                  ,                  K          -          1                                    (        4        )            Since the synthesizer output signal is the sum of all of the channel signals as shown in Equation 5, Equation 4 can be rewritten as shown in Equation 6:
                                          x            ^                    ⁡                      (            n            )                          =                              1            k                    ⁢                                    ∑                              k                =                0                                            k                -                1                                      ⁢                                                  ⁢                                                            x                  ^                                k                            ⁡                              (                n                )                                                                        (        5        )            
                                          x            ^                    ⁡                      (            n            )                          =                              ∑                          n              =                              -                ∞                                      ∞                    ⁢                                    f              ⁡                              (                                  n                  -                  mM                                )                                      ⁢                          1              K                        ⁢                                          ∑                                  k                  =                  0                                                  K                  -                  1                                            ⁢                                                                                          X                      ^                                        k                                    ⁡                                      (                    m                    )                                                  ⁢                                  W                  K                  kn                                                                                        (        6        )            
In order to improve the efficiency of such DFT filter banks, such DFT filter banks are known to be implemented as polyphase filters. More particularly, the decimator M and low pass filter h(n) implementation of the frequency analyzer and the interpolator M and filter f(n) of the frequency synthesizer are replaced with polyphase filter structures pρ (m) as illustrated in FIGS. 3A and 3B, respectively. As mentioned above, both the analyzer and the synthesizer are multirate devices. The complex modulation as well as the polyphase filters Pρ essentially shift the frequency of the prototype filters (h(n) or f(n)), for example as shown in FIG. 4. As shown, the center frequency of each of the M frequency channels is a multiple of the sampling frequency Fs, divided by the number of channels. As shown in FIG. 4, the transition bands of the low pass filter get shifted and become gaps in the frequency response of a DFT filter bank. In order to resolve this problem of gaps in the frequency response, DFT filter banks are utilized with stack shift capability. An example of such a DFT filter bank is illustrated in FIG. 5A, a polyphase filter bank with M channels, each channel including the following twiddle factors: tap twiddle, DFT twiddle and output twiddle, as discussed in detail Multi-Rate Digital Signal Processing, supra. Each tap twiddle factor includes a complex term in the form ej2πkom, wherein ko is the stack shift factor. The tap twiddle is used to provide the stack shift. Unfortunately, such a DFT filter bank with tap twiddle requires an inordinate amount of hardware to implement. For example, to implement an 8 phase 203 tap filter as illustrated in FIG. 5A, 211 selectable negators are required to produce even/odd stack shifts. Unfortunately, this amount of hardware duly complicates the system and raises the cost. Thus, there is a need for a more hardware efficient implementation of a digital filter bank with stack shift capability.